1. Field of the Invention
The present invention relates to a cache memory with a test function, and more particularly to a cache memory which is readily capable of testing a tag memory.
2. Description of Related Art
In a main storage of a computer system, microprocessor system or the like, there are stored an instruction code and data (hereinafter both referred to as data) necessary for operation processing. The data are read from the main storage as necessity requires when an address signal designating an address of the data, which is the location of the data being stored in the main storage, is given to the main storage. Such operation as reading the data from the main storage or writing and storing the data in the main storage is called access.
Incidentally, in the actual operation processing, the data read from the main storage is apt to be local. In other words, when the data was read from the main storage and was used, immediately afterward, this data is likely to be used repeatedly. The main storage has a large capacity, however, it operation speed is low, then, in the case where the main storage is to be accessed every time as necessity requires, it takes longer time for operation processing and this results in reducing the throughput of the whole system. In order to avoid such inconvenience, there has been put into practical use such an arrangement as that the data which was read from the main storage and its address in the main storage are temporarily stored in a memory which has a small capacity but operates at high speed, and such memory is accessed first when the next data is accessed, and in the case where any desired data is not stored in the memory, then the main storage is to be accessed. Such a memory as used on the above occasion is so called a cache memory.
FIG. 1 is a block diagram to illustrate by way of an example construction of such a cache memory as described above, which is disclosed in "Testing the MC 68030 Cache" 1987 ITC (Sept. 1987) pp. 826-833.
In the figure, a tag memory designated by reference numeral 1 stores therein the address, in a main storage (not shown), of the data stored in this cache memory. In this example, the tag memory 1 stores the high order bits A31 through A08 alone in 32 bits of addresses A31 through A00.
Reference numeral 2 designates a data memory which temporarily stores the data which was read from the main storage (not shown). As mentioned above, the high order bits of the address, in the main storage, of the data being stored in this data memory 2 are stored in the tag memory 1.
Reference numeral 3 designates a comparator which compares the high order bits A31 through A08 of the address to be accessed with the address stored in the tag memory 1. In the case where the address coincident with those high order bits A31 through A08 are stored in the tag memory 1, the comparator 3 turns a MISS signal to a low level, and where not, the comparator 3 turns the MISS signal to a high level.
Reference numeral 4 designates a tag memory updating control circuit which updates the content of the tag memory 1 as necessity requires.
Reference numeral 5 designates a transfer gate whose switching is controlled in response to the MISS signal outputted from the above-mentioned comparator 3. In other words, in the case where the compared result by the comparator 3 are coincident with each other, the MISS signal is turned to a low level to switch on the transfer gate 5. On the other hand, where those are not, the MISS signal is turned to a high level to switch off the transfer gate 5.
Reference numeral 70 designates a bus interface control circuit which controls operation of a bus interface circuit 7.
A bit array of an address of the data required to be accessed is schematically shown by reference numeral 8. This bit array consists of 32 bits A31 through A00.
The tag memory 1 is divided into 16 entries, each of which is specified and selected in response to four bits A07 through A04. The address bits A31 through A08 outputted from a CPU (not shown) are stored in this tag memory 1 by control of the tag memory updating control circuit 4 as necessity requires.
The data memory 2 consists of storing units of 64 words (32 bits per word) of 4 words.times.16 entries.
For the combination of the address and data to be accessed from an external circuit of the CPU or the like, the tag memory 1 stored the address bits A31 through A08 in its entries which were selected in response to the address signals A07 through A04. In response to the address signals A03, A02, one word is selected from among the four words being included in the selected block.
The whole functional operation of such a cache memory as described above is as follows.
When the CPU (not shown) accesses an instruction code to the main storage, the comparing circuit 3 compares the high order bits (A31-A08) of the address signal outputted from the CPU with the addresses being stored in the tag memory 1.
In the case where the coincident address with those high order bits is stored in the tag memory 1, which is called a cache hit, a word data which was selected in response to the address signals A07 through A04 and A03, A02 is read from the data memory 2 and is outputted to the CPU. In other words, the MISS signal is turned to a low level to switch on the transfer gate 5, and then the data is outputted from the data memory 2 via the transfer gate 5 and the bus interface circuit 7 to a data bus DB.
On the other hand, in the case where the coincident address with those high order bits is not stored in the tag memory 1, which is called a cache miss, the address signals A31 through A08 are stored in the tag memory 1 by control of the tag memory updating control circuit 4, and the word data whose high order 28 bits are coincident with the address of the accessed data is continuously stored in the data memory 2 via the bus interface circuit 7.
Such a tag memory 1 of the conventional cache memory is tested by the following process.
When implementing the most fundamental test of the tag memory 1, the bit pattern whose bits A31 through A08 are all "0" as shown by reference numeral 81 in FIG. 2, for example, is updated in an entry of the tag memory 1, and this bit pattern is tested to decide whether it is a cache hit or cache miss.
To be concrete, the bit pattern 81 coincident with the bit pattern of the updated address is judged to be a cache hit, and then data is outputted from the data memory 2, while it is confirmed that an access cycle to read data from the main storage will not be generated. And each of the bit patterns 82 different, by one bit alone, from the bit pattern of the updated address is judged to be a cache miss, and it is confirmed that an access cycle to fetch data from the main storage to the data memory 2 will be generated.
Furthermore, in the case where a cache miss is judged, the content of the address of the selected entry in the tag memory 1 was updated, then, it is necessary to reset the content of the selected entry in the tag memory 1 every time one cache miss is judged.
The conventional cache memory has thus been constructed, then, when a cache miss occurs, one data consisting of a plurality of words stored in the continuous addresses of the main storage after another is read in the data memory of the cache memory. As a result, the storage capacity of the cache memory itself tends to gradually increase, and when testing the cache memory, there exists a problem that the overhead will be longer when a cache miss is judged.
Furthermore, when the cache miss is judged, the content of the entry of tag memory to be tested is updated, then, it becomes necessary to reset the content of the tag memory every time a series of tests are finished. As a result, it takes longer time for carrying out the tests.
In addition to the above, there is a test method to make the whole content of the tag memory readable, however, this method necessitates a lot of additional circuits for test and more hardware equipment.